FIG. 1A is a schematic circuit diagram of a FinFET (Fin Field Effect Transistor) 6T (6 transistors) SRAM (Static Random Access Memory) device, as known in the prior art. The FinFET 6T SRAM device includes a first pull-up (PU) transistor 101, a first pull-down (PD) transistor 102, a first pass-gate (PG) transistor 105, a second PU transistor 103, a second PD transistor 104, and a second PG transistor 106. First PG transistor 105 has a source terminal connected to a bit line (BL), second PG transistor 106 has a source connected to BLB. BL and BLB are complementary signals. The gate terminals of the first and second PG transistors are connected to a word line (WL).
In a read operation, the work line is asserted high, the drain terminal and the source terminal of first PG transistor 105 are connected, and the drain terminal and the source terminal of second PG transistor 106 are connected. For example, a node 11 stores data “0,” since the first PU transistor and the first PD transistor form a first inverter, and the second PU transistor and the second PD transistor form a second inverter, a node 12 stores data “1”, so that the drain terminal and the source terminal of first PD transistor are connected, and the drain terminal and the source terminal of first PU transistor are not connected. When the bit line BL is connected to a high voltage level (referred to as logic “1” hereinafter), the charge of the bit line BL is transferred through first PG transistor 105 to node 11 (e.g., storing data “0”), generating thus a current IPG, and through first PD transistor 102 to ground VSS, generating thus a current IPD, thereby performing a discharge. At this point, the bit line BL is going from high to low, data “0” is read. For the complimentary bit line BLB, which is connected to a low voltage level (referred to as logic “0” hereinafter), the “0” storing at node 11 turns on second PU transistor 103 to connect the source terminal to the drain terminal of second PU transistor and turns off second PD transistor 104 so that its source terminal is not connected to its drain terminal. The high voltage level “1” of the voltage source Vdd flows toward the complementary bit line BLB, turning the low voltage level of the complementary bit line BLB to a high voltage level. As it can be seen, the larger the current IPD is with regard to IPG
      (                  i        .        e        .            ,                        the          ⁢                                          ⁢          greater          ⁢                                          ⁢          the          ⁢                                          ⁢          ratio          ⁢                                          ⁢          β                =                              I            PD                                I            PG                                )    ,the higher is the charge flowing from the bit line BL through the PG transistor to node 11, and as much as possible flowing to ground VSS, so that there is no charge accumulation at node 11, thereby reducing interference at the node to achieve a better read noise margin.
In a write operation, if node 11 stores data “0,” then node 12 stores data “1.” In a write operation, such as to write a “1” to node 11, the stored “0” will become a “1.” The bit line BL is asserted high, the complementary bit line BLB is asserted low. The word line WL is asserted high, the drain terminal and the source terminal of second PG transistor 106 are connected, generating thus a current I′G flowing from node 12 to the complementary bit line BLB. Since node 11 stores data “0,” the source terminal and the drain terminal of second PU transistor 103 are connected, generating a current IPU flowing from the voltage source Vdd to node 12. The greater the current I′PG with regard to the current IPU is, the faster the data “1” stored in node 12 can be pulled toward “0,” the “1” of node 12 becomes “0”. The source terminal and the drain terminal of first PU transistor 101 are connected, so that the high voltage level “1” changes the “0” of node 11 to “1”, and the write operation is complete. As it can be seen, the larger the current I′PG is with regard to IPU
      (                  i        .        e        .            ,                        the          ⁢                                          ⁢          greater          ⁢                                          ⁢          the          ⁢                                          ⁢          ratio          ⁢                                          ⁢          γ                =                              I            PG            ′                                I            PU                                )    ,the faster the write operation can be complete to achieve a better write margin.
However, conventional FinFET 6T SRAM devices have small β and γ ratios, resulting in a poor read noise margin and write margin.
FIG. 1B is a layout of a FinFET 6T SRAM device, as known in the prior art. As shown in FIG. 1B, the ratio of the number of Fins of the respective PU, PD, and PG transistors of the FinFET 6T SRAM device is PU:PD:PG=1:2:2, since the ratio of the amount of current flowing through each transistor is equal to the number of Fins of the corresponding turned-on FinFET transistor, the β ratio may be realized by the ratio of the number of Fins of PD and PG transistors, i.e.,
      β    =                  PD        PG            =                        2          2                =        1              ,the β ratio of 1 provides a poor read noise margin. This is because a smaller β ratio means that the charge from the bit line BL (e.g., data “1”) through the PG transistor to reach node 11 (e.g., data “0”) does not completely flow from the PD transistor to ground VSS, node 11 may have a charge accumulation resulting in interference at the node.
FIG. 1C is another layout of a FinFET 6T SRAM device, as known in the prior art. As shown in FIG. 1C, the ratio of the number of Fins of the PU, PD, and PG transistors of the FinFET 6T SRAM device is PU:PD:PG=1:2:1,
      β    =                  PD        PG            =                        2          1                =        2              ,thereby achieving a better read noise margin, however, this layout will produce some side effects. Since the ratio of the amount of current flowing through each transistor is equal to the number of Fins of the corresponding turned-on FinFET transistor, the γ ratio can be realized by the ratio of PG and PU Fin transistors, i.e.,
      γ    =                  PG        PU            =                        1          1                =        1              ,the γ ratio of 1 provides a poor write margin. This is because a smaller γ ratio will make the process of changing from the original data “1” of node 11 to “0” of the bit line BL relatively slow.
Thus, there is a need to solve the problems of poor read noise margin and poor write margin of conventional FinFET 6T SRAM devices.